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TC9496AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9496AF
1 Chip Audio Digital Signal Processor
TC9496AF is the 1 chip audio DSP which built in 24-bits, a 22.5 MIPS DSP core, 3 ch AD converter, 5 ch DA converter, and electronic volume for trims, and corresponds to a Multi-speaker system. It is possible to realize many application, such as sound field control-hall simulation, for example-, digital filter for equalizers, dynamic range control, KARAOKE and something.
Features
* Incorporates 3 ch AD converter, 2 ch is 1 bit - type AD converter for HiFi-Audio and 1 ch is 16 bit Multi-bit type AD converter for Microphone. 2 ch HiFi-ADC (1 bit- type) S/N: 96dB (typ.) 1 ch Mic. ADC (16 bit Multi-bit type) S/N: 80dB (typ.) * Incorporates 1 bit- type DA converter, and the attenuator for trims is built in each DAC output. In case of the use which does not use a trim, It is possible to output the analog signal of DAC directly. 5 ch DAC (1 bit- type) S/N: 96dB (typ.) Attenuator for trim 0dB to -24dB (1dB step) * * Each port has a digital input/output. A built-in self-boot function automatically sets the coefficients and register values at initialization. Moreover, four kinds of boot data can be chosen by pin setup. Boot ROM: 1024 word x 18 bit * The DSP block specification are as follows: Data bus: 24 bit Multiplier/adder: 24 bit x 16 bit + 43 bit 43 bit Accumulator: 43 bit (sign extension: 4 bit) Program ROM: 2048 word x 32 bit Coefficient RAM: 448 word x 16 bit Coefficient ROM: 256 word x 16 bit Offset RAM: 64 word x 16 bit Data RAM: 256 word x 24 bit Operation speed: 44 ns (510-step (approx.) operation per cycle at fs = 44.1 kHz) Interface buffer RAM: 32 word x 16 bit * * * * Incorporates data delay RAM of 64 kbit. Delay RAM: 4096 word x 16 bit (64 kbit) The microcontroller interface can be selected between TOSHIBA original 3 line type and I2C bus format. CMOS silicon structure supports high speed. The package is a 100-pin flat package. Weight: 1.57 g (typ.)
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Block Diagram/Pin Connection
BA0
BA1
I2CS ERR
IFOK
IFDO IFDI
IFCK CS
GND
DOUT DIN
EBCI
EBCO ELRI
ELRO
SYNC VDD
BOOT
RESET STEP0
STEP1 EM1
EM0
TP15
TP14 VDD
MCK
TP13 GND
(QFP 100 pin) Top View
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 CKO1 Self Boot D-IN/OUT CKO0 48 FS 47 TP12 46 TP11 45 TP10 44 TP9 43 TP8 42 TP7 41 TP6 Unfolding ADC (Lch) Moving average filter Decimation Filter Interpolation Filter 40 TP5 39 GNDR 38 37 ADC (Rch) SD SD SD SD DAC (Lch) ATT 256 fs ATT ATT ATT DAC (Rch) DAC (Cch) DAC (SLch) SD 36 TP4 35 TP3 DAC (SRch) ATT 32 TP0 31 NC 34 TP2 33 TP1 VDDR NC Delay RAM 4 k word 16 bit ADC (MIC) ASP (audio signal processor) 49 MCU I/F Timing Gen.
50
NC
82
TST0
83
TST1
84
TST2
85
TST3
86
VDM
87
VRM1
MIC-IN
88
MIN
89
MOUT
90
VRM2
91
GNDM
92
VSAL
Lch-IN
93
LIN
94
AVRL
95
VDL
96
VDR
97 256 fs Timing Gen.
AVRR
Rch-IN
98
RIN
99
VSAR
100
GNDX
1 XO VDX AOL AILT AOR AIRT AOLT VRLR AORT VDALR GNDAL GNDAR
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AOC AICT VRO VRI AOCT VRCS AISLT AOSL AOSR AISRT VDACS +5 V Rch-OUT Cch-OUT SLch-OUT SRch-OUT AOSLT GNDAC GNDASL GNDASR AOSRT VDASR +5 V
XI +5 V Lch-OUT
+5 V
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Pin Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol XI XO VDX GNDAL AOL AOLT VRLR AILT VDALR AIRT AORT AOR GNDAR GNDAC AOC AOCT VRCS AICT VRO VRI VDACS AISLT AOSLT AOSL GNDASL GNDASR AOSR AOSRT AISRT VDASR NC TP0 TP1 TP2 TP3 TP4 NC VDDR GNDR TP5 I/O I O 3/4 3/4 O O 3/4 I 3/4 I O O 3/4 3/4 O O 3/4 I O I 3/4 I O O 3/4 3/4 O O I 3/4 3/4 O O O O O 3/4 3/4 3/4 O Function Crystal oscillator connecting or external clock input pin Crystal oscillator connecting pin Power pin for oscillator circuit Ground pin for DAC Left channel DAC Left channel signal output pin DAC Left channel attenuator output pin Reference voltage pin for DAC L/R channel DAC Left channel attenuator input pin Power pin for DAC L/R channel DAC Right channel attenuator input pin DAC Right channel attenuator output pin DAC Right channel signal output pin Ground pin for DAC Right channel Ground pin for DAC Center channel DAC Center channel signal output pin DAC Center channel attenuator output pin Reference power pin for DAC C/SL/SR channel DAC Center channel attenuator input pin Reference voltage pin for attenuator (buffer output) Reference voltage pin for attenuator (buffer input) Power pin for DAC C/SL channel DAC SL channel attenuator input pin DAC SL channel attenuator output pin DAC SL channel signal output pin Ground pin for DAC SL channel Ground pin for DAC SR channel DAC SR channel signal output pin DAC SR channel attenuator output pin DAC SR channel attenuator input pin Power pin for DAC SR channel Non-Connecting Test pin 0 Test pin 1 Test pin 2 Test pin 3 Test pin 4 Non-Connecting Power pin for delay RAM Ground pin for delay RAM Test pin 5 Select the open state, VDD connecting or GND connecting Select the open state, VDD connecting or GND connecting Remarks
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Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Symbol TP6 TP7 TP8 TP9 TP10 TP11 TP12 FS CKO0 CKO1 GND TP13 MCK VDD TP14 TP15 EM0 EM1 STEP1 STEP0
RESET
I/O O O O O O O O O O O 3/4 O O 3/4 O O I I I I I 3/4 I I I I I I O 3/4 I I I Test pin 6 Test pin 7 Test pin 8 Test pin 9 Test pin 10 Test pin 11 Test pin 12
Function
Remarks
Clock out pin (sampling frequency) Clock output pin 0 Clock output pin 1 Ground pin Test pin 13 MCK clock output pin Power pin Test pin 14 Test pin 15 De-emphasis setting pin 0 De-emphasis setting pin 1 ASP execution step switching pin 1 ASP execution step switching pin 0 Reset pin Power pin Program synchronous signal input pin LR clock input pin for serial data output (DOUT) LR clock input pin for serial data input (DIN) Bit clock input pin for serial data output (DOUT) Bit clock input pin for serial data input (DIN) Serial data input pin Serial data output pin Ground pin Microcontroller interface chip select signal input pin Microcontroller interface data shift clock signal input pin 3 line bus mode: Microcontroller interface data input pin I C bus mode: Microcontroller interface data input/output pin Microcontroller interface data output pin Microcontroller interface operation flag pin Error flag output pin Microcontroller interface I C bus/3 line bus switching pin Boot address setting pin 1 Boot address setting pin 0 Self boot control pin Non-connecting Test pin T0 Schmitt input Schmitt input Schmitt input Select the open state, VDD connecting or GND connecting Schmitt input
2 2
Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input
VDD SYNC ELRO ELRI EBCO EBCI DIN DOUT GND
CS
Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input
Schmitt input Schmitt input Schmitt input/ Open drain output
IFCK IFDI
I/O IFDO IFOK
ERR
O O O I I I I 3/4 I
Open drain output Open drain output
I2CS BA1 BA0 BOOT NC TST0
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Pin No. 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol TST1 TST2 TST3 VDM VRM1 MIN MOUT VRM2 GNDM VSAL LIN AVRL VDL VDR AVRR RIN VSAR GNDX I/O I I I 3/4 3/4 I O 3/4 3/4 3/4 I 3/4 3/4 3/4 3/4 I 3/4 3/4 Test pin T1 Test pin T2 Test pin T3 Power pin for microphone ADC Reference voltage pin 1 for microphone ADC Microphone ADC amplifier input pin Microphone ADC amplifier output pin Reference voltage pin 2 microphone ADC Ground pin for microphone ADC Ground pin for ADC L channel ADC L channel signal input pin Reference voltage pin for ADC L channel Power pin for ADC L channel Power pin for ADC R channel Reference voltage pin for ADC R channel ADC R ch signal input pin Ground pin for ADC R channel Ground pin for oscillator circuit Function Remarks Schmitt input Schmitt input Schmitt input
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Operation
1. Pin Operation
Pin No. 1 2 3 to 30 31 32 to 36 37 38 39 40 to 47 48 Symbol XI XO Omitted NC 3/4 Non-connecting. Select the open state, VDD connecting or GND connecting. Connect the crystal oscillator. Function
TP0 to TP4 Test pin. (leave open) NC VDDR GNDR TP5 to TP12 FS Non-connecting. Select the open state, VDD connecting or GND connecting. Power pin for delay RAM Ground pin for delay RAM Test pin (leave open) Clock out pin (sampling frequency) Timing output pins. The output frequency is set from the microcontroller (command-40h) Command (set the command-40h) CKOS02 0 CKOS01 0 0 1 1 0 0 1 1 CKOS00 0 1 0 1 0 1 0 1 Command (set the command-40h) CKOS12 0 0 0 0 1 1 1 1 CKOS11 0 0 1 1 0 0 1 1 CKOS10 0 1 0 1 0 1 0 1
CKO0 Output Frequency Fixed to L fs 2 fs 4 fs 8 fs 16 fs 32 fs 64 fs 128
CKO1 Output Frequency Fixed to L fs 2 fs 4 fs 8 fs 16 fs 32 fs 64 XI 1/2
49 50
CKO0 CKO1
0 0 0 1 1 1 1
51 52
GND TP13
Ground pin Test pin (leave open) Master clock output pin. Validated/Invalidated of an output, and the frequency is switched from in the of microcontroller command (command-4Dh) and STEP1 pin (59 pin).
Command (set the command-4Dh) MCKE 53 MCK 0 1 1 1 Note 1: Don't care 54 55 56 VDD TP14 Test pin (leave open) TP15 Power pin 0 1 1 MCKS
Pin STEP1
MCK Output
(Note 1) (Note 1) (Note 1) 0 1
Fixed to L fs 256 Source oscillation (XI) Prohibited
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Pin No. Symbol De-emphasis control pins Function
EM1 57 58 EM0 EM1 0 0 1 1
EM0 0 1 0 1
De-Emphasis Setting De-emphasis off fs = 48 kHz fs = 44.1 kHz fs = 32 kHz
Source oscillation frequency/ASP operation speed switching pins Source Oscillation Frequency fs 512 fs 768 Prohibited No. of ASP Operation Steps 340/fs 510/fs
STEP1 59 60 STEP1 STEP0 0 0 1
STEP0 0 1 *
61 62 63 64
RESET
Reset pin. L at initialization. Power pin Program operation SYNC signal input pin. LR clock signal input pin for serial output data.
VDD SYNC ELRO
Valid when serial data are output in a slave operation (set the command-4Dh). LR clock signal input pin for serial input data. 65 ELRI Valid when serial data are input in a slave operation (set the command-4Dh). Bit clock signal input pin for serial output data. 66 EBCO Valid when serial data are output in a slave operation (set the command-4Dh). Bit clock signal input pin for serial input data. 67 EBCI Valid when serial data are input in a slave operation (set the command-4Dh). Serial input data signal input pin. Connected to internal register in ASP block. 68 DIN The internal register connected is set up by the microcomputer command (command-43h). Serial input data signal input pin. Connected to internal register in ASP block. 69 70 DOUT The internal register connected is set up by the microcomputer command (command-43h). GND Ground pin
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Pin No. Symbol Microcontroller interface pins. Function
I2CS 0 71 72 73 74 75 76 77
CS
Transmission Mode Standard Transmission mode I C mode
2
1
IFCK IFDI IFDO IFOK
ERR CS
Standard Transmission Mode Chip select Transmit/receive clock Data or command input Data output (monitor mode) Error flag signal output Internal operation confirmation flag signal output
I C Mode Chip select (can be fixed to L) Transmit/receive clock Data input/output Fixed to L output Error flag signal output Internal operation confirmation flag signal output
2
IFCK IFDI IFDO
ERR
I2CS
IFOK
Self-boot start address setting pins (at reset)
BA1 78 79 BA1 BA0 0 0 1 1
BA0 0 1 0 1
Start Address 000h 001h 002h 003h
Self-boot control pin
BOOT 80 BOOT 0 1
Operation Does not Self-boot at reset Self-boot at reset
81 82 to 85 86 to 100
NC TST0 to TST3 Omitted
Non-connecting. Select the open state, VDD connecting or GND connecting. Test pin. Use fixed to L. 3/4
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2. Microcontroller interface
2.1 Standard Transmission Mode
When I2CS = L, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock, the IFDI signal is the data. The TC9496AF loads the IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care.
2.1.1 Setting Registers
CS
IFCK IFDI
C7 C5 C3 C1 C0 D15 D13 D11 D9 D14 D12 D10 D8 D7 D5 D3 D1 D0
Don't care IFOK
C6
C4
C2
D6
D4
D2
Don't care
Cn: COMMAND Dn: Data
The registers are set by command data using IFDI signal. The first byte is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB. Data are loaded the rising edge of the IFCK signal. Note that commands or data that must be switched, such as the RUN-MUTE command (command-44h) or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
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2.1.2 Setting RAM (sequential)
CS
IFCK
IFDI
A15 A13 A11 A9 A14 A12 A10 A8 A6 A4 A2 A0 D14 D12 D10 D8 D0 A7 A5 A3 A1 D15 D13 D11 D9 D1 C0
C7
C5
C3
C1
Don't care IFOK Cn: COMMAND An: ADDRESS Dn: Data
C6
C4
C2
Don't care
The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field following the RAM address bytes is 2 n bytes. The address is automatically incremented by 1. During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal. Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [s] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP, it is written in asynchronous.
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2.1.3 Setting RAM (ACMP mode)
CS
IFCK
IFDI
A15 A13 A11 A9 A14 A12 A10 A8 A6 A4 A2 A0 D14 D12 D10 D8 D6 D4 D2 D0 D0 A7 A5 A3 A1 D15 D13 D11 D9 D7 D5 D3 D1 D1 C0
C7
C5
C3
C1
Don't care IFOK
C6
C4
C2
Don't care
Cn: COMMAND An: ADDRESS Dn: Data
(1)
(2)
In ACMP mode, the TC9496AF does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC9496AF is operating. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words. < The length of the data field is 2 n bytes, where n = 32. In ACMP mode, the IFOK pin outputs an ACMP operation end flag. When ACMP operations complete, the flag is set to LOW ((1)) and is initialized at the next low chip select signal ((2)). Operation at the time of transmitting other commands, before IFOK terminal was set to "L" level cannot be guaranteed. Please set up again after initializing by RESET terminal or the initialization command.
K6 + K9 MCU-I/F IFB-RAM CRAM Update for 1 fs K4 K7
K1
+
K2
Write one by one K5 K8 K10
K3
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2.1.4 Monitor Mode
CS
IFCK
IFDI
D22 D20 D18 D16 D23 D21 D19 D17 D15 D13 D11 D9 D7 D5 D3 D1 D14 D12 D10 D8 D6 D4 D2 D0
C7
C5
C3
C1
Don't care
C6
C4
C2
C0
Don't care
IFDO
IFOK
(1)
Cn: COMMAND Dn: DATA
Monitor mode is used to monitor the data bus or pointers. There are two further modes: a mode where the data bus or pointer (s) is monitored at a present program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to PC. After the command is issued, when the TC9496AF loads data to the IFDO register (IFDOR), the IFOK pin signal is set to LOW (see (1) above). Next, when the IFCK signal is sent, the data are output on the IFCK signal falling edge starting from the MSB. The data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. In cases where transfer must be interrupted, such as where only eight or 16 bits of the MSB side are required, monitoring can be interrupted at any time by setting the CS signal to High, the IFOK signal also goes High.
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2.2 I C Bus Mode
When I2CS = H, data can be transmitted or received in I2C bus mode. When the CS signal is Low, control from the microcontroller is enabled. In I2C mode, the CS signal can be used fixed to L. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9496AF loads the IFDI data on the IFCK signal rising edge. When CS = H, IFCK and IFD signal are don't care.
2
2.2.1 Setting Registers
start
CS
32h
HZ
HZ
HZ
HZ
end
IFCK IFDI (MCU (R)) IFCK An: I C ADDRESS Cn: COMMAND Dn: Data
2
A7
A5
A3
A1
C7
C5
C3
C1 C0
D15 D13 D11 D9 D14 D12 D10 D8
D7
D5
D3
D1 D0
A6
A4
A2 A0
C6
C4
C2
D6
D4
D2
The register are set by command data using the IFDI signal. The first byte after the I2C address (= 32h) is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C format. The data loaded internally every two bytes. Note that commands or data that must be switched on the SYNC signal, such as the RUN command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal.
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2.2.2 Setting RAM (sequential)
HZ HZ HZ HZ HZ HZ end
start
32h
CS
IFCK
IFDI (MCU (R))
C7
RA15 RA13 RA11 RA9 RA14 RA12 RA10 RA8
A7 C6 C4 C2 C0 RA6 RA4 RA2 RA0 D14 D12 D10 D8
A5
A3
A1
C5
C3
C1
RA7 RA5 RA3 RA1
D15 D13 D11 D9
A6
A4
A2 A0
IFCK Cn: COMMAND 2 An: I C ADDRESS RAn: RAM-ADDRESS Dn: Data
The RAMs are set by command data using the IFDI signal. The first byte after the I2C address (= 32h) is a command, which differs for each RAM. The next two bytes contain the start address for each RAM. The length of the data field following the RAM address bytes is 2 n bytes. The address is automatically incremented by 1. During program running, 1 word of data is written at a time in internal RAM synchronizing with a SYNC signal. Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [s] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP, it is written in asynchronous.
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2.2.3 Setting RAM (ACMP mode)
HZ HZ HZ HZ HZ HZ end 32h HZ
CS
start
32h
IFCK
IFDI (MCU (R))
C7
RA15 RA13 RA11 RA9 RA14 RA12 RA10 RA8
A7 C6 C4 C2 C0 RA6 RA4 RA2 RA0 D14 D12 D10 D8 A4
A5
A3
A1
C5
C3
C1
RA7 RA5 RA3 RA1
D15 D13 D11 D9
A3
A1
A6
A4
A2 A0
A2 A0
IFOK
2
An: I C ADDRESS Cn: COMMAND RAn: RAM-ADDRESS Dn: Data
(1)
(2)
In ACMP mode, the TC9496AF does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC9496AF is operating. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32-words. < The length of the data field is 2 n bytes, where n = 32. In ACMP mode, the IFOK pin outputs an ACMP operation end flag. When ACMP operations complete, the flag is set to LOW ((1)) and is initialized at the next low chip select signal ((2)). Operation at the time of transmitting other commands, before IFOK terminal was set to "L" level cannot be guaranteed. Please set up again after initializing by RESET terminal or the initialization command.
K1 + K4 K7 K9 +
K6
K2
MCU-I/F
IFB-RAM
CRAM Update for 1 fs
Write one by one K5 K8 K10
K3
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2.2.4 Monitor Mode
end start end
CS
start
IFCK ID = 33h
IFDI (MCU (R)) COMMAND (50h to 57h)
ID = 32h
IFDI (TC9496AF (R)) IFOK (1)
Monitor mode is used to monitor the data bus or pointers. There are two further modes: a mode where the data bus or pointer (s) monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. First, issue the monitoring command, which has no data. When the TC9496AF loads data to the IFDO register (IFDOR), the IFOK pin signal is set to LOW (see (1) above). Next, the I2C read command (ID = 33h) is issued, then when the IFCK signal is sent, the data are output on the IFCK signal falling edge from the MSB. The data length is at its maximum (24 bits or three byte) during monitoring of the data bus. Although it is possible per byte to read only 8 or 16 bits by the side of MSB, MCU has to make it the number of bytes which specified I2COS of command 4Bh at that time. After issuing a monitor command (50h to 56h), be sure to perform a continuous read operation by issuing the I2C read comman (ID = 33h).
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2.3
IFOK Pin Description
The IFOK signal has the following three functions.
2.3.1 ACMP Mode End Flag Output
After the completion of a RAM data update with CRAM-ACMP (command-47h) or OFRAM-ACMP (command- 49h), the IFOK pin goes Low. Setting the CS signal to Low changes the IFOK signal from Low to High.
Example:
CS
IFCK CRAM-ACMP any command
IFDI
IFOK Update complete Next Command
Don't care
8 clock
16 clock
16 clock
2.3.2 Loading End Flag Output in Monitor Mode
When monitoring using the bus monitor command (command-50h), for example, after data are loaded to the internal register under the specified conditions, the IFOK signal goes Low. In this mode, if CS signal is made into "H" level, IFOK signal will also be set to "H" level.
Example:
CS
IFCK any command data
IFDI
MON-DB
IFDO
IFOK Internal register loading end
Don't care
16 clock
16 clock
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2.3.3 Attenuator Operation End Flag Output of the Digital-Filter Section
When using a command to control the DF block mute ON/OFF (command-44h, bit5), the mute end flag is output from the IFOK pin after the mute operation completes. Moreover, when the amount of attenuators by DF attenuator command (command-58h) is changed, IFOK terminal is set to "L" level as a flag which attenuator operation completed.
CS
IFCK MUTE any command
IFDI
MUTE
IFOK ATT = 100% Next Command 16 clock 16 clock MUTE OFF ATT = 0% Next Command
Don't care MUTE ON 8 clock
ATT
100%
0% 1 fs 1024 (23 ms @ fs = 44.1 kHz) 1 fs 1024
Note At power on, the IFOK pin output is undefined. When the CS signal goes Low, the IFOK signal goes High.
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3. Control Commands
The following table lists the control commands that can be used from the microcontroller.
3.1
Control Commands
Table 1
Command TIMING BOOT DAC-LR SIO RUN-MUTE MSEQ CRAM CRAM-ACMP ORAM ORAM-ACMP IFF MONI-PC MONI-LC MISC 3/4 M-RST Code 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh W R/W Timing
Control Commands
RAM Sequential 3/4 3/4 3/4 3/4 3/4 Transfer Sync/ Async to SYNC Signal Async Async Async Async Sync Sync: RUN/Async: STOP
Description
Self Boot ROM start address DAC output trim level (L, R) SIO setting Program execution, mute Sequential RAM CRAM CRAM (ACMP mode) ORAM ORAM (ACMP mode) IFF setting Monitor: PC condition Monitor: LC condition Others Prohibited Initialization
Enable
Async Sync: RUN/Async: STOP Async
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Sync Async Async Async 3/4 Async
MONI-DB MONI-CP MONI-OFP MONI-DP MONI-AR MONI-CRP MONI-SR
50h 51h 52h 53h 54h 55h 56h R
DBUS monitor CP monitor OFP monitor DP monitor AR monitor CRP monitor SR monitor
Async Async Async Async Async Async Async
DF-ATT DAC-S DAC-C
58h 59h 5Ah W
DF attenuator level (all channel) DAC output trim level (SL, SR-ch) DAC output trim level (C-ch)
Async Async Async
Note 2: The command which is "Sync" in the transfer Sync with Sync signal needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command. (It need more than 22.68 ms at fs = 44.1 KHz.)
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3.2 Commands Description
Each command explanation is shown below. * mark in each command explanation table shows the initial value at the time of reset.
Command-40h (0100 0000): TIMING
D15 D14 D13 D12 D11 SYA1 D10 SYA0 D9 SYPS D8 SYS1 D7 SYS0 D6 0 D5 D4 D3 D2 D1 D0
SYPD SYD1
SYD0 SYPA
CKOS CKOS CKOS CKOS CKOS CKOS 12 11 10 02 01 00
Bit D15
Name SYPD
Description ASP digital block sync polarity switching
Value 0* 1 0*
Operation ASP program starts on falling edge ASP program starts on rising edge Signal after SYNC output SYNC pin ELRI pin ELRO pin DF-processing starts in a falling DF-processing starts in a rising Signal after SYNC output SYNC pin ELRI pin ELRO pin Operates at polarity for SYPD, SYPA settings above. Reverses all polarities for SYPD, SYPA settings above. Internal SYNC signal SYNC pin ELRI pin ELRO pin 3/4 Fixed to L output fs2 (internal fs 2) fs4 (internal fs 4) fs8 (internal fs 8) fs16 (internal fs 16) fs32 (internal fs 32) fs64 (internal fs 64) Output XI divided by 2 Fixed to L output fs2 (internal fs 2) fs4 (internal fs 4) fs8 (internal fs 8) fs16 (internal fs 16) fs32 (internal fs 32) fs64 (internal fs 64) fs128 (internal fs 128)
D14 D13
SYD [1:0]
ASP digital block SYNC signal input switching
1 2 3
D12
SYPA
DF block sync polarity switching
0* 1 0*
D11 D10
SYA [1:0]
DF block SYNC signal input switching
1 2 3
D9
SYPS
Overall system sync polarity switching
0* 1 0*
D8 D7
SYS [1:0]
SYNC circuit input signal switching selection
1 2 3
D6
3/4
Fixed to 0 (zero)
3/4 0* 1 2
D5 CKOS1 D4 [2:0] D3 CKO1 (50 pin) pin output selection 3 4 5 6 7 0* 1 2 D2 CKOS0 D1 [2:0] D0 CKO0 (49 pin) pin output selection 3 4 5 6 7
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TC9496AF
Command-41h (0100 0001): BOOT
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 BTA9 D8 BTA8 D7 BTA7 D6 BTA6 D5 BTA5 D4 BTA4 D3 BTA3 D2 BTA2 D1 BTA1 D0 BTA0
Bit D9 to D0
Name BTA
Description
Value
Operation
Self-boot ROM start address [9:0]
000h to Starts self-boot operation from specified address 3FEh
Command-42h (0100 0010): DAC-LR
D15 0 D14 0 D13 0 D12 ATTL 4 D11 ATTL 3 D10 ATTL 2 D9 ATTL 1 D8 ATTL 0 D7 0 D6 0 D5 0 D4 ATTR 4 D3 D2 D1 ATTR 1 D0 ATTR 0
ATTR ATTR 3 2
Bit D12 to D8
Name ATTL [4:0]
Description
Value 00h to 1Fh* Code: ATT (dB): Initial value: Code: ATT (dB): Initial value: 00h 0 1Fh 00h 0 1Fh 01h -1 01h -1
Operation 02h -2 18h 19h 1Fh -24 ca.-60 ca.-60 1Fh 02h -2 18h 19h 1Fh -24 ca.-60 ca.-60
DAC L channel attenuator value
D4 to D0
ATTR [4:0]
DAC R channel attenuator value
00h to 1Fh*
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TC9496AF
Command-43h (0100 0011): SIO
D15 CHSI D14 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ISLT1 ISLT0 IBCS1 IBCS0 IFMT1 IFMT0
CHSO CHSO OSLT 1 0 1
OSLT OBCS OBCS OFMT OFMT 0 1 0 1 0
Bit D15 D14
Name CHSI 3/4
Description Serial input (SI) switching Fixed to 0 (zero)
Value 0* 1 3/4 0* 16 slots (bit clock = 32 fs) 20 slots (bit clock = 40 fs) 24 slots (bit clock = 48 fs) 32 slots (bit clock = 64 fs) 16 bits 18 bits 20 bits 24 bits Pads from the beginning Pads from the end I2S format 3 0 DOUT pin SO0 register DOUT pin SO1 register DOUT pin SO2 register 16 slots (bit clock = 32 fs) 20 slots (bit clock = 40 fs) 24 slots (bit clock = 48 fs) 32 slots (bit clock = 64 fs) 16 bits 18 bits 20 bits 24 bits Pads from the beginning Pads from the end I2S format 3
Operation SI0 register ADC, SI1 register DIN pin SI1 register ADC, SI0 register DIN pin 3/4
D13 D12
ISLT Number of serial input slots [1:0]
1 2 3 0*
D11 D10
IBCS Serial input bit length [1:0]
1 2 3 0*
D9 D8
IFMT Serial input format [1:0]
1 2
D7 D6
CHSO Serial output (SO) switching [1:0]
1 2* 3 0*
D5 D4
OSLT Number of serial output slots [1:0]
1 2 3 0*
D3 D2
OBCS Serial output bit length [1:0]
1 2 3 0*
D1 D0
OFMT Serial output format [1:0]
1 2
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Command-44h (0100 0100): RUN-MUTE
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 RUN D6
MADOFF
D5
DFMUTE
D4 0
D3
IMUTE
D2
D1
D0
OMUTE OMUTE OMUTE 2 1 0
Bit D15 to D8 D7
Name 3/4
Description
Value 3/4 0* Stops program Runs program Microphone ADC ON Microphone ADC OFF Mute OFF Mute ON
Operation 3/4
Fixed to 0 (zero)
RUN
ASP program execution 1 0*
D6
MADOFF
Microphone ADC OFF 1 0
D5 D4 D3
DFMUTE 3/4 IMUTE
DF block mute 1* Fixed to 0 (zero) ASP block input mute (SI0, SI1 register mute) ASP block output mute 3/4 0 1* 0 1* 0 1* 0 1* Mute OFF Mute ON Mute OFF Mute ON Mute OFF Mute ON Mute OFF Mute ON 3/4
D2
OMUTE2 (SO2 register mute) ASP block output mute
D1
OMUTE1 (SO1 register mute) ASP block output mute
D0
OMUTE0 (SO0 register mute)
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Command-45h (0100 0101): MSEQ
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
MSA3 MSA2 MSA1 MSA0
Bit D3 to D0
Name MSA [3:0]
Description Module sequential RAM first address
Value 0h to Fh
Operation
The address of the head to write in is set up.
D15 0
D14 0
D13 0
D12 0
D11 0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ MSEQ 10 9 8 7 6 5 4 3 2 1 0
Bit D10 to D0
Name MSEQ
Description
Value
Operation
Module sequential RAM data [10:0]
000h The data written in module sequence RAM are set up. (PC value to at the time of SQRET) 7FFh
Data are sent continuously after transmitting the module sequence RAM head address (2 bytes). Enable a sequential write to RAM. 45h-MSEQ RAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes) (module sequential RAM: 16 words)
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Command-46h (0100 0110): CRAM
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CRAMA 0
CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA 9 8 7 6 5 4 3 2 1
Bit D9 to D0
Name CRAMA [9:0]
Description CRAM (coefficient RAM) head address
Value
Operation
000h CRAM address of the head at the time of writing in by 46h to command is set up. 1BFh
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit D15 to D0
Name CRAMD
Description
Value
Operation
CRAM data [15:0]
7FFFh to Set CRAM data (two-complement-form formula) 8000h
The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 46h-CRAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
Command-47h (0100 0111): CRAM-ACMP
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CRAMA 0
CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA CRAMA 9 8 7 6 5 4 3 2 1
Bit D9 to D0
Name CRAMA [9:0]
Description
Value
Operation
CRAM first address
000h CRAM address of the head at the time of writing in by 47h to command is set up. 1BFh
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD CRAMD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit D15 to D0
Name CRAMD
Description
Value
Operation
CRAM data [15:0]
7FFFh to Set CRAM data (two-complement-form formula) 8000h
It is CRAM write-in command which used the address compare mode. A maximum of 32 words is written at once. The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 47h-CRAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes)
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Command-48h (0100 1000): ORAM
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0
ORAMA ORAMA ORAMA ORAMA ORAMA ORAMA 5 4 3 2 1 0
Bit D5 to D0
Name ORAMA
Description
Value 00h to 3Fh
Operation ORAM address of the head at the time of writing in by 48h command is set up.
ORAM first address [5:0]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit D15 to D0
Name ORAMD
Description
Value 7FFFh to 0000h
Operation
ORAM data [15:0]
Set ORAM data
The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 48h-ORAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes) (ORAM: 64 word)
Command-49h (0100 1001): ORAM-ACMP
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0
ORAMA ORAMA ORAMA ORAMA ORAMA ORAMA 5 4 3 2 1 0
Bit D5 to D0
Name ORAMA [5:0]
Description
Value 00h to 3Fh
Operation ORAM address of the head at the time of writing in by 49h command is set up.
ORAM first address
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD ORAMD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit D15 to D0
Name ORAMD
Description
Value 7FFFh to 0000h
Operation
ORAM Data [15:0]
Set ORAM data (two-complement-form formula)
It is ORAM write-in command which used the address compare mode. A maximum of 32 words is written at once. The data written in continuously are sent after transmitting ORAM head address (2 bytes) Enable a sequential write to RAM. 49h-ORAM address (2 bytes)-Data (2 bytes)-Data (2 bytes)-........-Data (2 bytes) (ORAM: 64 word)
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Command-4Ah (0100 1010): IFF
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 IFF2 D1 IFF1 D0 IFF0
Bit D2 to D1
Name IFF [2:0] Set IFFn
Description
Value 0* 1 IFFn = 0 IFFn = 1
Operation
n = 2, 1, 0
Command-4Bh (0100 1011): MONI-PC
D15 D14 D13 0 D12 0 D11 0 D10 MPC 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2COS I2COS 1 0
MPC9 MPC8 MPC7 MPC6 MPC5 MPC4 MPC3 MPC2 MPC1 MPC0
Bit D15 to D14 D13 to D11 D10 to D0
Name I2COS [2:0]
Description
2
Value 0h to 3h
Operation Set the data byte length when monitoring in I C mode. Code: 3h Byte: 3 byte 2h 2 byte 1h, 0h 1 byte 3/4
2
Monitor data length in I C mode
3/4 MPC [10:0]
Fixed to 0 (zero)
3/4
Monitor condition (command-50h to 56h)
000h Set the Program Counter (PC) conditions (PC value) when to carrying out a monitor by command-50h to 56h. 7FFh
Command-4Ch (0100 1100): MONI-LC
D15 0 D14 0 D13 0 D12 0 D11 0 D10 LCE D9 LCS D8 LCDE D7 LCD7 D6 LCD6 D5 LCD5 D4 LCD4 D3 LCD3 D2 LCD2 D1 LCD1 D0 LCD0
Bit D15 to D11 D10
Name 3/4
Description
Value 3/4 0* 1 0
Operation 3/4 Does not add LC value to the conditions. Adds LC value to the condition. Compares with LC0 value. Compares with LC1 value. After a match, does not change the value to be compared with the LC. After a match, automatically decrements by -1 the value to be compared with the LC. Set the LC conditions (loop counter value) when carrying out a monitor by command-50h to 56h.
Fixed to 0 (zero) Whether LC (loop counter) value applied to monitor conditions or not. LC selection
LCE
D9
LCS
1 0 D8 LCDE Automatic LC decrement 1 D7 to D0 LCD [7:0] Value in comparison with the loop counter when carrying out a monitor 00h to FFh
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Command-4Dh (0100 1101): MISC
D15 0 D14 0 D13 0 D12 0 D11 0 D10 SIS D9 SOS D8
ERDET
D7 ZST
D6
D5
D4
D3
D2
D1
D0 0
DP7F SYRC SYRO MCKE MCKS DLSEP
Bit D15 to D11 D10
Name 3/4
Description
Value 3/4 0*
Operation 3/4 Master (synchronized with the internal clock) Slave (synchronized with the external clock (ELRI, EBCI)) Master (synchronized with the internal clock) Slave (synchronized with the external clock (ELRO, EBCO)) Invalid Valid 2-cycle access 1-cycle access 256 word 128 word Does not reset Reset Does not reset Reset Disable (fixed to L) Enable (output ) 256 fs Source oscillation Does not use table Use 2-k word area as the table 3/4
Fixed to 0 (zero)
SIS
Serial Input 1 0*
D9
SOS
Serial output 1 0
D8
ERDET
Error detection 1* Switches to access CROM using Log-Linear adjustment 128/256 word of DRAM (DATA RAM) switching Set CP at each SYNC 1* 0 0 1* 0* 1 0
D7
ZST
D6
DP7F
D5
SYRC
D4
SYRO
Set OFP at each SYNC 1* 0
D3
MCKE
MCK pin output enable 1* 0
D2
MCKS
MCK pin output switching 1* Delay RAM table area switching Fixed to 0 (zero) 0 1* 3/4
D1 D0
DLSEP 3/4
Command-4Fh (0100 1111): M-RST
D15 MRST D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
Bit D15 D14 to D0
Name MRST
Description Initialization from the micro controller command
Value 0* 1 3/4 Does not initialize
Operation
Initializes (set to initial value.) 3/4
3/4
Fixed to 0 (zero)
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Command-50h (0101 0000): MON-DB
O 23 DB 23 O 22 DB 22 O 21 DB 21 O 20 DB 20 O 19 DB 19 O 18 DB 18 O 17 DB 17 O 16 DB 16 O 15 DB 15 O 14 DB 14 O 13 DB 13 O 12 DB 12 O 11 DB 11 O 10 DB 10 O9 DB 9 O8 DB 8 O7 DB 7 O6 DB 6 O5 DB 5 O4 DB 4 O3 DB 3 O2 DB 2 O1 DB 1 O0 DB 0
Bit O23 to O0
Name DB
Description
Value
Operation
Data bus monitor [23:0]
000000h to Reads data bus on the condition: Command-4Bh, 4Ch FFFFFFh
Command-51h (0101 0001): MON-CP
O 23 0 O 22 0 O 21 0 O 20 0 O 19 0 O 18 0 O 17 0 O 16 0 O 15 0 O 14 0 O 13 0 O 12 0 O 11 0 O 10 0 O9 0 O8 0 O7 CP 7 O6 CP 6 O5 CP 5 O4 CP 4 O3 CP 3 O2 CP 2 O1 CP 1 O0 CP 0
Bit O23 to O9 O8 to O0
Name 3/4 CP [8:0]
Description
Value 3/4
Operation 3/4
Fixed to 0 (zero)
CP monitor (coefficient RAM pointer)
000000h to Reads CP on the condition: Command-4Bh, 4Ch 0001BFh
Command-52h (0101 0010): MON-OFP
O 23 0 O 22 0 O 21 0 O 20 0 O 19 0 O 18 0 O 17 0 O 16 0 O 15 0 O 14 0 O 13 0 O 12 0 O 11 0 O 10 0 O9 0 O8 0 O7 0 O6 0 O5 O4 O3 O2 O1 O0
QFP QFP QFP QFP QFP QFP 5 4 3 2 1 0
Bit O23 to O6 O5 to O0
Name 3/4 OFP [5:0]
Description
Value 3/4
Operation 3/4
Fixed to 0 (zero)
OFP monitor (offset RAM pointer)
000000h to Reads OFP on the condition: Command-4Bh, 4Ch 00003Fh
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Command-53h (0101 0011): MON-DP
O 23 0 O 22 0 O 21 0 O 20 0 O 19 0 O 18 0 O 17 0 O 16 0 O 15 0 O 14 0 O 13 0 O 12 0 O 11 0 O 10 0 O9 0 O8 0 O7 DP 7 O6 DP 6 O5 DP 5 O4 DP 4 O3 DP 3 O2 DP 2 O1 DP 1 O0 DP 0
Bit O23 to O8 O7 to O0
Name 3/4 DP [7:0]
Description
Value 3/4
Operation 3/4
Fixed to 0 (zero)
DP monitor (data RAM pointer)
000000h to Reads DP on the condition: Command-4Bh, 4Ch 0000FFh
Selection (DP0/DP1/DP2/DP3) of DP is DP chosen by command executed at the time of PC set up as conditions.
Command-54h (0101 0100): MON-AR
O 23 0 O 22 0 O 21 0 O 20 0 O 19 0 O 18 0 O 17 0 O 16 0 O 15 0 O 14 0 O 13 0 O 12 0 O 11 AR 11 O 10 AR 10 O9 AR 9 O8 AR 8 O7 AR 7 O6 AR 6 O5 AR 5 O4 AR 4 O3 AR 3 O2 AR 2 O1 AR 1 O0 AR 0
Bit O23 to O12 O11 to O0
Name 3/4 AR [11:0]
Description
Value 3/4
Operation 3/4
Fixed to 0 (zero)
AR monitor (delay RAM address)
000000h Reads delay RAM address on the condition: Command-4Bh, to 4Ch 000FFFh
Command-55h (0101 0101): MON-CRP
O 23 0 O 22 0 O 21 0 O 20 0 O 19 0 O 18 0 O 17 0 O 16 0 O 15 0 O 14 0 O 13 0 O 12 0 O 11 0 O 10 0 O9 0 O8 O7 O6 O5 O4 O3 O2 O1 O0
CRP CRP CRP CRP CRP CRP CRP CRP CRP 8 7 6 5 4 3 2 1 0
Bit O23 to O9 O8 to O0
Name 3/4 CRP [8:0]
Description
Value 3/4
Operation 3/4
Fixed to 0 (zero)
CRP monitor (CROM pointer)
000000h to Reads CRP on the condition: Command-4Bh, 4Ch 0001FFh
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Command-56h (0101 0110): MON-SR
O 23 0 O 22 0 O 21 0 O 20 0 O 19 0 O 18 0 O 17 0 O 16 0 O 15 0 O 14
LRF
O 13 GF 3
O 12 GF 2
O 11 GF 1
O 10
O9
O8
O7
O6
O5
O4
O3
O2
O1 ZF
O0 SF
GF LI LG OV OV RD RD V1F V0F 0 -LG -LI -1E -0E -23 -16
Bit O23 to O15 O14 to O0
Name 3/4
Description
Value 3/4
Operation 3/4
Fixed to 0 (zero) SR monitor
SR (status register)
3/4
Reads SR on the condition: Command-4Bh, 4Ch
Command-58h (0101 1000): DF-ATT
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 ATL6 D5 ATL5 D4 ATL4 D3 ATL3 D2 ATL2 D1 ATL1 D0 ATL0
Bit
Name
Description
Value
Operation Initial value: 7Fh (level = 0dB) LEVEL = 20 log (ATL/128)
Code 7Fh 7Eh 7Dh ~ D6 to D0 ATL DF attenuator value [6:0] 00h to 7Fh* 72h 65h 5Ah ~ 40h ~ 02h 01h 00h
Level 0.00dB -0.14dB -0.21dB ~ -1.01dB -2.06dB -3.06dB ~ -6.02dB ~ -36.12dB -42.14dB -dB
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Command-59h (0101 1001): DAC-S
D15 0 D14 0 D13 0 D12 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 D3 D2 D1 D0
ATTSL ATTSL ATTSL ATTSL ATTSL 4 3 2 1 0
ATTSR ATTSR ATTSR ATTSR ATTSR 4 3 2 1 0
Bit D12 to D8
Name ATTSL
Description
Value 00h to 1Fh* Code: ATT (dB): Initial value: Code: ATT (dB): Initial value: 00h 0 1Fh 00h 0 1Fh 01h -1 01h -1
Operation 02h -2 18h 19h 1Fh -24 ca.-60 ca.-60
DAC SL-ch attenuator value [4:0]
D4 to D0
ATTSR DAC SR-ch attenuator value [4:0]
00h to 1Fh*
02h -2
18h 19h 1Fh -24 ca.-60 ca.-60
Command-5Ah (0101 1010): DAC-C
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 ATTC 4 D3 D2 D1 ATTC 1 D0 ATTC 0
ATTC ATTC 3 2
Bit D4 to D0
Name ATTC
Description
Value 00h to 1Fh* Code: ATT (dB): Initial value: 00h 0 1Fh 01h -1
Operation 02h -2 18h 19h 1Fh -24 ca.-60 ca.-60
DAC C-ch attenuator value [4:0]
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4. Self-Boot Function Description
4.1 Self-Boot Function
The TC9496AF supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later. The microcontroller interface circuit supports two format: I2C and the original mode. However, the boot must be executed in Standard Transmission. All the command inputs from the exterior are disregarded during a boot term.
RESET
Self-boot circuit BTCSN BTIFCK BTIFDI BTMODE
Microcontroller interface circuit
CS IFCK IFDI
BOOT BA1 BA0
SBROM (1024 word 18 bit)
Timing gener -ator
1 0 Internal CSN
1 0 Internal IFCK
1 0 Internal IFDI
Internal I2CS
I2CS
Figure 1
Self-Boot System
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4.2 Boot ROM Format
The following shows the brake down of the 18 bits.
00 01 10 11 Data that are being sent Command Final data (after the data are sent, the CS signal is set to "H"). Jump address (jump to any address in the self-boot ROM).
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (MSB) 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 11 11 11 11 01 10 01 00 00 00 00 10 11 Data Data Data Data Data Address Data CMD Address Address Address Address CMD (LSB) JMP JMP JMP JMP CMD Data (last) CMD Data (cont) Data (cont) Data (cont) Data (cont) Data (last) JMP 3FFh
3FFh
11
Address
JMP 3FFh
Figure 2
Boot ROM Format and Example
Note 3: Boot mode completes when the address reaches 3FFh, the maximum value. Therefore, for the final address, write JMP 3FFh (data = 303FFh).
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4.3 Self-Boot Operation
Self-boot operations support two modes: one for use at reset and for setting the microcontroller. The modes can be used in combination.
4.3.1 Self-Boot Operation
To enter this mode, set the Boot pin to High, then set the RESET pin to Low or send initialized command. The 2048 fs period (46.4 ms when fs = 44.1 kHz) after a reset release is wait period. The boot operation starts at the end of this period. When switching the setting according to application, specify the start address using the BA [1:0] pin. At addresses 000h to 002h, set jump addresses. The data setting speed is one of SBROM per 1 fs. As up to 1024 words can be set in the SBROM, the maximum time required for setting the data is the 1024 fs period.
Table 1
fs 32 kHz 44.1 kHz 48 kHz
Relationship between fs and Wait Period
Wait Period 64.0 ms 46.4 ms 42.7 ms Boot Time (max.) 32.0 ms 23.2 ms 21.3 ms
Table 2
BA1 0 0 1 1
Relationship between BA [1:0] Pin Value and Start Address
BA2 0 1 0 1 Start Address 000h 001h 002h 003h
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4.3.2 Self-Boot Operation when Setting Microcontroller
In this mode, the microcontoroller can specify any address and the boot operation starts from that address. The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the BOOT command (command: 41h) from the microcontroller starts the boot operation with no wait. The boot operation when set from the microcontroler is the same as the self-boot operation at reset except that the boot operation can start from any address.
Boot wait period 2048 fs /RST FS Fixed to "H" BOOT BTMODE (internal signal) BA [1:0] BootRom Adrs Rom Dt [17:16] BTCSN BTIFCK BTIFDI C D D D C D C DT: Data DE: DataEnd 2 2 JMP 10 11 12 13 14 15 16
CMD
Boot time 1024 fs (max)
3FF
JMP
DT DT DE
CMD
DE
CMD
JMP
8 clock
C
Figure 3
Boot Timing Chart (at reset)
Table 3
Parameter Boot Wait Period Boot Start Address BOOT pin
Differences Depending on Operation Mode
RESET Pin or Initialized Command
BOOT Command No Any address specified from microcontroller Any (don't care)
Yes Select from 000h to 003h with BA0 and BA1 terminal "H" Level
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TC9496AF
4.4 Programming Examples
The following shows the programming example in Self-boot mode. 000: 30040h jmp 040h ; Jump to 040h 001: 30100h jmp 100h ; Jump to 100h 002: 30200h jmp 200h ; Jump to 200h 003: 30004h jmp 004h ; Jump to 004h 004: 10040h cmd 40h ; Command 40h (TIMING) 005: 28007h data 8007h ; CKOS0 = 7 (fs128 output) 006: 10043h cmd 43h ; Command 43h (SIO) 007: 20039h date 0039h ; CHSO = 0 (SO0), OSLT = 3 (32 bit), OBCS = 2 (20 bit), OFMT = 1 (padded from the end) 008: 10045h cmd 45h ; Command 45h (MSEQ) 009: 00000h data 0000h ; Start address = 0h 00A: 00001h data 0001h ; MSEQ [0] = 001h 00B: 00123h data 0123h ; MSEQ [1] = 123h 00C: 20320h data 0320h ; MSEQ [2] = 320h 00D: 30300h jmp 300h ; Jump to 300h : 100: 10046h cmd 46h ; Command 46h (CRAM) 101: 00000h data 0000h ; Start address = 0h 102: 00000h data 0000h ; CRAM [0] = 0000h 103: 00000h data 0000h ; CRAM [1] = 0000h 104: 00000h data 0000h ; CRAM [2] = 0000h 105: 20000h data 0000h ; CRAM [3] = 0000h 106: 30380h jmp 380h ; Jump to 380h : 300: 10046h cmd 46h ; Command 46h (CRAM) 301: 00000h date 0000h ; Start address = 0h 302: 07FFFh data 7FFFh ; CRAM [0] = 7FFFh 303: 08000h data 8000h ; CRAM [1] = 8000h 304: 03FFFh data 3FFFh ; CRAM [2] = 3FFFh 305: 24000h data 4000h ; CRAM [3] = 4000h 306: 30380h jmp 380h ; Jump to 380h : 380: 10046h cmd 46h ; Command 46h (CRAM) 381: 00080h data 0080h ; Start address = 80h 382: 0FFFEh data FFFEh ; CRAM [80h] = FFFEh 383: 2FFFFh data FFFFh ; CRAM [81h] = FFFFh 384: 303FFh jmp 3FFh ; Jump to 3FFh : 3FF: 303FFh jmp 3FFh ; Jump to 3FFh
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5. Cautions on Use
5.1 Initial Reset
After a power-supply injection, once at least, please set up a required register after applying reset which makes RESET terminal "L" level and making the value of an internal register data.
5.2
The Cautions at the Time of Using IFOK Terminal
The timing which outputs IFOK signal is the signal which shows whether the command received from the microcomputer was performed normally. Since the initial value of IFOK signal is unfixed when a control microcomputer is checking IFOK signal, before sending a command, it may stop performing control from a microcomputer.
5.3
The Cautions at the Time of Using ACMP (address compare mode)
In rewriting coefficient data and offset data using ACMP mode, please do not use it the following condition.
5.3.1 Please do not Transmit the Following Command before Completing Rewriting of Data.
Please do not send the following command before completing rewriting of data of CRAM or ORAM. Please check that waiting the term after rewriting has been completed until it transmits the following command was carried out, or rewriting has been completing using IFOK signal.
5.3.2 Please do not Include Data of an Intact Address.
Please do not include coefficient data of offset data of address which are not used by the program under execution, into transmitting data. When data of an intact address is contained, operation in ACMP mode cannot de ended. If the following command is transmitted in this state, RAM data will become unfixed also by the command with the command unrelated to CRAM or ORAM. It needs to reset and all data needs to be reset up to interrupt before completing rewriting of data in the rewriting processing.
5.3.3 Please do not Perform Continuation Transmission Over the 0 Address.
The transmission over the 0th address may incorrect-operate. The same of this restriction is said not only of ACMP mode but continuation transmission of usual RAM data. For example, when writing in 1B8h from 1BFh and 007h from 000h or CRAM, it must transmit in two steps.
th
5.4
The Handling of NC Terminal
Please use NC terminal by either of the following. 31 pin and 37 pin * Open (non-connection) * * Connect to VDD Connect to GND
81 pin * Open (non-connection) * Connect to VDD
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Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD Vin PD Topr Tstg Rating -0.3 to 6.0 -0.3 to VDD + 0.3 1500 -40 to 75 -55 to 150 Unit V V mW C C
(unless otherwise noted, Ta = 25C, VDD = VDX = VDDR = VDM = VDL = VDR = VDX = VDAL = VDAR = VDAC = VDAS = VDASR = 5.0 V) DC Characteristics
Characteristics Operating power supply voltage Operating frequency range Symbol VDD fopr IDD Test Circuit 3/4 3/4 3/4 Test Condition Ta = -40 to 75C 340 step mode 511 step mode fopr = 36.864 MHz, 511-step mode Min 4.75 8 12 3/4 Typ. 5.0 15 33.8 150 Max 5.25 25 MHz 37 165 mA Unit V
Electrical Characteristics
Operating power supply current
Clock pins (XI, XO)
Characteristics "H" level Input voltage (1) "L" level "H" level Output voltage (1) "L" level VIL1 VOH1 VOL1 IOH = -3.0 mA IOL = 5.0 mA Symbol VIH1 3/4 XI pin Test Circuit Test Condition Min VDD 0.7 3/4 VDD - 0.5 3/4 Typ. 3/4 3/4 3/4 3/4 Max VDD + 0.3 VDD 0.3 3/4 0.5 V Unit
V
3/4
XO pin
Input Pins
Characteristics "H" level Input voltage (2) "L" level Input leakage current "H" level "L" level VIL2 IIH2 IIL2 3/4 VIN = VDD VIN = 0 V (Note 4) (Note 5) Symbol VIH2 3/4 (Note 4) Test Circuit Test Condition Min VDD 0.8 3/4 3/4 -10 Typ. 3/4 3/4 3/4 3/4 Max 3/4 V VDD 0.2 10 3/4 mA Unit
Note 4: STEP0 to 1, RESET , SYNC, ELRO, ELRI, EBCO, EBCI, DIN, EM0 to 1, I2CS, CS , IFCK, IFDI, BOOT, BA0 to BA1, TST0 to 3 (normally input pins and schmitt input pins) Note 5: XI
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Output Pins
Characteristics "H" level "L" level Output voltage (3) "L" level Output open leakage current Symbol VOH2 VOL2 VOL3 IOZ4 3/4 3/4 Test Circuit 3/4 Test Condition IOH = -2.0 mA IOL = 2.0 mA IOL = 4.0 mA VOH = VDD (Note 7) (Note 7) Min VDD - 0.5 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 Max 3/4 0.5 0.5 10 V mA Unit
Output voltage (2)
(Note 6)
V
Note 6: FS, CKO0 to 1, MCK, DOUT, IFDO (normally output) Note 7: IFDI (when I C mode output), IFOK, ERR (open drain output)
2
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AC Characteristic
AD Converter (1): LIN, RIN pins
Characteristics Symbol Test Circuit 3/4 3/4 3/4 Test Condition Input level that ADC output at full-scale digital output (Note 8) LIN, RIN pins A-Weight, X'tal: 36.864 MHz (Note 8) S/Na2 3/4 CCIR-ARM, X'tal: 36.864 MHz (Note 8) THD + N THDa 3/4 20 kHz LPF, X'tal: 36.864 MHz (Note 8) Cross-talk CTa 3/4 20 kHz LPF, X'tal: 36.864 MHz (Note 8) Dynamic range DRa 3/4 A-Weight, X'tal: 36.864 MHz (Note 8) 85 92 3/4 dB 3/4 -90 -83 dB 3/4 -80 -72 dB 85 93 3/4 dB (Note 8) Min Typ. Max 3/4 3/4 3/4 Unit
Maximum input signal level Input impedance
Vi Zin S/Na1
1.18 3/4 88
1.27 27 96
Vrms kW dB
S/(N + D) ratio
Note 8: Input channels: LIN, RIN
AD Converter (2): MIN pin
Characteristics Symbol Test Circuit 3/4 3/4 3/4 Test Condition Input level that ADC output at full-scale digital output (Note 9) MIN pin A-Weight, X'tal: 36.864 MHz (Note 9) THD + N THDaM 3/4 20 kHz LPF, X'tal: 36.864 MHz (Note 9) CTaM1 Cross-talk CTaM2 3/4 X'tal: 36.864 MHz MIN (R) LIN, RIN (Note 10) Dynamic range DRaM 3/4 A-Weight, X'tal: 36.864 MHz (Note 9) 70 80 3/4 dB 3/4 -90 -83 dB 3/4 X'tal: 36.864 MHz LIN, RIN (R) MIN (Note 10) 3/4 -76 -60 dB 3/4 -62 -53 dB (Note 9) Min 3/4 3/4 70 Typ. Max Unit
Maximum input signal level Input impedance S/(N + D) ratio
ViM ZinM S/NaM
1.1 1 80
1.15 3/4 3/4
Vrms kW dB
Note 9: Input channels: MIN Note 10: Input channels: LIN, RIN, MIN
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DA Converter
Characteristics Output signal level S/Nratio THD + N Cross-talk Dynamic range Symbol Ao S/Nd THDd CTd DRd Test Circuit 3/4 3/4 3/4 3/4 3/4 Test Condition Output voltage at full-scale (Note 10) digital input A-Weight, X'tal: 36.864 MHz 20 kHz LPF, X'tal: 36.864 MHz 20 kHz LPF, X'tal: 36.864 MHz A-Weight, X'tal: 36.864 MHz Min 1.23 90 3/4 3/4 87 Typ. 1.33 98 -84 -90 95 Max 1.43 3/4 -75 -83 3/4 Unit Vrms dB dB dB dB
Timing
Clock Input Pins (XI)
Characteristics Clock cycle Clock "H" cycle width Clock "L" cycle width Symbol tXI tXIH tXIL Test Circuit 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 Min 29 3/4 3/4 Typ. 3/4 14.5 14.5 Max 3/4 3/4 3/4 Unit ns ns ns
Reset Pin ( RESET )
Characteristics Standby time Reset pulse width Symbol tRRS tWRS Test Circuit 3/4 3/4 Test Condition 3/4 3/4 Min 10 1.0 Typ. 3/4 3/4 Max 3/4 3/4 Unit ms ms
Timing Output
Characteristics CKO output delay time Symbol tDFC Test Circuit 3/4 Test Condition 3/4 Min -150 Typ. 3/4 Max 150 Unit ns
Audio Serial Interface (EBCI, DIN, EBCO, DOUT)
Characteristics ELRI hold time DIN setup time DIN hold time EBCI clock cycle EBCI clock "H" cycle width EBCI clock "L" cycle width ELRO hold time DOUT output delay time (1) DOUT output delay time (2) EBCO clock cycle EBCO clock "H" cycle width EBCO clock "L" cycle width Symbol tLIH tSDI tHDI tEBCI tEBIH tEBIL tLOH tDO1 tDO2 tEBCO tEBOH tEBOL Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Min -75 50 50 300 150 150 -75 3/4 3/4 300 150 150 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 75 3/4 3/4 3/4 3/4 3/4 75 60 60 3/4 3/4 3/4 Unit ns ns ns ns ns ns ns ns ns ns ns ns
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Microcontroller Interface
(1) Standard transmission mode ( CS , IFCK, IFDI, IFDO)
Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CL = 30 pF 3/4 3/4
Characteristics Standby time
CS (fall)-IFCK (fall) setup time
Symbol tSTB tCCD tWLC tWHC tCKC tWCS tSCD tHCD tDDO
Test Condition 3/4 3/4 3/4 3/4 3/4 (Note 11)
Min 1.0 0.2 0.25 0.25 0.2 0.5 0.2 0.2 3/4
Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Max 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.2
Unit ms ms ms ms ms ms ms ms ms
IFCK "L" cycle width IFCK "H" cycle width IFCK (rise)- CS (rise) setup time
CS "H" cycle time
IFDI-IFCK (rise) setup time IFCK (rise)-IFDI hold time IFCK (fall)-IFDO propagation delay time
Note 11: The command which is "Sync" in the transfer Sync with Sync signal of a 19 page table 1 control command table needs to set the CS = H section to a minimum of 1 fs more until it transmits the follwing command. (It needs more than 22.68 ms at fs = 44.1 KHz.) I2C mode ( CS , IFCK, IFDI)
Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
(2)
Characteristics IFCK clock frequency IFCK "H" cycle width IFCK "L" cycle width Data setup time Data hold time Transmission start condition hold time Repeat transmission start setup time Transmission end condition setup time Data transmission interval I C rising time I C falling time
2 2
Symbol tIFCK tH tL tDS tDH tSCH tSCS tECS tBUF tR tF
Test Condition CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF
Min 0 0.6 1.3 0.1 0 0.6 0.6 0.6 1.3 3/4 3/4
Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Max 400 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.3 0.3
Unit kHz ms ms ms ms ms ms ms ms ms ms
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AC Characteristic Measurement Point
(1) Clock Pin (XI)
XI 50% tXIH tXI tXIL
(2)
Reset
100% VDD 0%
RESET
90%
50% tRRS tWRS
(3)
Timing output
100% FS 0% 50%
CKO0 to 1 tDFC
50%
(4)
Audio serial interface (ELRI, EBCI, DIN, ELRO, EBCO, DOUT)
tEBCI tEBIL ELRI tEBIH
EBCI
DIN
tLIH
tSDI
tHDI
tLIH
tEBCO tEBOL ELRO tEBOH
EBCO
DOUT
tLOH
tDO1
tDO2
tLOH
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(5) Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO)
RESET
CS
tSTB tCCD
CS
tWLC
tWHC
tCKC
tWCS
IFCK
IFDI tSCD IFDO tDDO tHCD
(6)
Microcontroller interface in I2C mode (IFCK, IFDI)
tBUF
IFDI
IFCK
tSCH
tR
tL
tH
tDS
tDH
tSCS
tF
tECS
Purchase of Toshiba I2C components conveys a license under the Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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Peripheral Circuit Example
Audio I/F 4.7 kW 4.7 kW MCU I/F
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
47 mF 0.1 mF 47 mF 0.1 mF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CS BA0 BA1 IFDI DIN VDD EM1 ERR GND EM0 VDD ELRI I2CS IFCK IFOK EBCI MCK TP15 IFDO ELRO DOUT BOOT EBCO SYNC STEP0 RESET STEP1 TP14 TP13 GND CKO1 50 CKO0 49 FS 48 TP12 47 TP11 46 TP10 45 TP9 44 TP8 43 TP7 42 TC9496AF (top view) TP6 41 TP5 40 0.1 mF GNDR 39 VDDR 38 NC 37 TP4 36 TP3 35 TP2 34 TP1 33 TP0 32 GNDASL GNDASR NC 31 GNDAC VRCS VRO VRI VDACS AOC AOCT AICT AISLT AOSLT AOSL AOSR AOSRT AISRT VDASR 3.3 mF 47 mF 0.1 mF 0.1 mF 0.1 mF 0.1 mF 47 mF 0.1 mF 270 W 10 mF 10 kW AOLTch Output AORTch Output AOCTch Output AOSLTch Output 10 kW AOSRTch Output 10 mF 270 W 2200 pF 10 mF 10 mF 10 mF 2200 pF 3.3 mF 47 mF
81 NC 82 TST0 83 TST1 84 TST2 85 TST3 47 mF 87 VRM1 88 MIN 89 MOUT 90 VRM2 91 GNDM 92 VSAL 39 kW 94 AVRL 95 VDL 96 VDR 97 AVRR 98 RIN 99 VSAR
100 GNDX
0.1 mF 86 VDM
47 mF
MIC Input 2200 pF 47 mF 47 mF 93 LIN
4.7 mF 10 kW
10 kW
560 pF 47 mF
1200 pF 18 kW
10 kW
50 W
Lch Input
4.7 mF
0.1 mF
2200 pF
Rch Input
4.7 mF
2200 pF
1 kW
0.1 mF
47 mF
47 mF
1 kW
XO
VDX
VRLR
VDALR
AOL
AOLT
AILT
AIRT
AORT
XI
47 mF
3.3 mF
50 W
3.3 mF
47 mF
47 mF
1
2
3
GNDAL
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3.3 mF 47 mF 47 mF
0.1 mF 2.2 MW 10 pF 3.3 mF 47 mF 36.8 MHz 27 pF
47 mF
AOR
GNDAR
47 mF
1000 pF 2200 pF
270 W
270 W
10 kW
10 kW
10 kW
270 W 2200 pF 2200 pF
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Package Dimensions
Weight: 1.57 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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